1. Field of the Invention
The present invention relates to a delay circuit and an improved oscillation circuit which has the same structure as the delay circuit and which is designed for use in a semiconductor integrated circuit. The invention further relates to a semiconductor memory device which comprises an oscillator having the same structure as the improved oscillator.
2. Description of the Related Art
Delay circuits of various structures have been provided. Among them are delay circuits which incorporate MOS transistors. Delay circuits having the following structure have been known.
FIG. 1 shows a first example of the delay circuit which incorporate MOS transistors.
The delay circuit shown in FIG. 1 is set in standby state while an input signal Vin remains at low level, and in active state while the input signal Vin remains at high level. While the circuit assumes the standby state, the capacitor C4 is charged to the supply voltage Vcc by the p-channel transistor Qp17, and the output signal Vout is therefore at low level. When the input signal Vin rises to high level, the capacitor C4 is discharged through the n-channel transistor Qn20. The input potential of the inverter I8 (i.e., the voltage on the capacitor C4) is thereby lowered from high level to low level. The moment the input potential of the inverter I8 falls below the threshold voltage of the inverter I8, the output signal Vout rises from low level to high level. The time which lapses until the output signal Vout rises to high level after the input signal Vin has risen to high level is equal to the time which lapses until the input potential of the inverter I8 falls from the supply voltage Vcc to the threshold voltage of the inverter I8. This time is the delay time.
To prevent the delay time from changing with the fluctuation of the supply voltage Vcc, the inverter I8 comprises an n-channel transistor and a p-channel transistor whose current-drivability is greater than that of the n-channel transistors. The threshold voltage of the inverter I8 is therefore nearly equal to (Vcc-Vt), where Vt is the threshold voltage of the p-channel transistor Qp17. The voltage Vt is constant, not depending upon the supply voltage Vcc. The delay time is given as a time of which the storage node of the capacitor C4 is changed from the initial value Vcc to the threshold voltage (Vcc-Vt) of the inverter I8. As described above, the charge to be discharged is proportional to Vt which does not depend on the Vcc, thereby Vcc dependency of the delay time is reduced. The voltage applied to the gate of the n-channel transistor Qn20 to discharge the capacitor C4 is the supply voltage Vcc while the delay circuit remains in active state. The discharge ability of the n-channel transistor Qn20 depends on its gate voltage (i.e., the supply voltage Vcc). Hence, the delay time depends upon the supply voltage Vcc.
The above delay circuit has a disadvantage in that its operating characteristic is affected by the characteristic differences which the transistors have inevitably because of the existing manufacturing technology. More specifically, the n-channel transistors have threshold voltages different from the design values and therefore discharging abilities different from the desired values. The p-channel transistor may fail to have the desired threshold voltage. Accordingly, the charge which these transistors discharge from the capacitor C4 and which determines the delay time may change from the design value.
The longer the delay time the delay circuit has, the larger the element area the capacitor C4 and the n-channel transistor Qn20 need to have. Furthermore, the capacitor C4 or the n-channel transistor Qn20, or both must have a large element area. This is because the input potential of the inverter I8 is nothing more than a change in the threshold voltage Vt of the p-channel transistor Qp17.
FIG. 2 shows another known delay circuit having MOS transistors, which is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 3-23709. This delay circuit has a delay time which is relatively constant despite the changes in the supply voltage Vcc and in the threshold voltages of the p-channel transistors.
The output of the delay circuit, however, has sloping trailing edges. The delay time inevitably changes in accordance with the threshold voltage of an inverter circuit which receives the output of the delay circuit. To be more precise, although the delay time is relatively constant, it varies since the threshold voltage of the inverter circuit changes due to the fluctuation of the supply voltage Vcc and/or that of the conductances of the transistors forming the inverter circuit.
FIG. 3 illustrate a known delay circuit which provides two or more delay times. This delay circuit generates output signals Vout1, Vout2, . . . , Voutn, the waveforms of which are shown in FIG. 4.
The delay circuit has delay units 40 as many as the delay times it provides. The number of the elements constituting the delay circuit is the number of delay units 40 multiplied by the number of elements forming each delay unit 40. Obviously, the area occupied by all elements of the delay circuit is enormous.
FIG. 5 shows another known delay circuit which provides two or more delay times. The delay circuit generates output signal Vout, the waveform of which is shown in FIGS. 6A and 6B. The circuit shown in FIG. 5 can change the delay time according to a command signal CMD. When the command signal CMD is at low level, the delay units 60, which have delay times T1 and T2, respectively, are connected in series, and the output signal Vout rises to high level upon lapse of a time (T1+T1) from the time after the input signal Vin has risen to high level, as illustrated in FIG. 6A. When the signal CMD is at high level, the output of only the delay unit T1 is valid, and the output signal Vout rises to high level upon lapse of a time (T1) time after the input signal Vin has risen to high level, as shown in FIG. 6B. The delay circuit may have three or more delay units 60, instead of two delay units 60 as shown in FIG. 5.
The more delay times the circuit needs to provide, more delay units 60 it should have. The more delay units 60, the larger the area the elements of the delay circuit will occupy.
As mentioned above, the delay time of a delay circuit varies if the supply voltage, threshold voltage of the transistors, and/or that of the conductances of the MOS transistors fluctuate. On the other hand, a delay circuit obtaining a large delay time must have a large element area and a large consumption current.
An oscillation circuit for use in semiconductor integrated circuits may comprise a two-input NAND gate the first input of which is connected to receive an input signal (e.g., a signal Vin), and a plurality of inverters the outputs of which are fed back to the second input of the NAND gate. The oscillation remains in standby state as long as the input signal is at low level. It starts performing its function when the input signal rises from low level to high level. The oscillating frequency of the circuit varies not only with the supply voltage but also with the changes in the characteristics of the transistors it incorporates.
Known as one type of an EEPROM into which data can be written and from which data can be erased by using a single power source (e.g., Vcc=5 V) is, for example, a NAND-type EEPROM. A NAND-type EEPROM has a memory cell array ordinarily provided in a p-type well formed in either a p-type substrate or n-type substrate. The memory cell array comprises a plurality of cell units connected to bit lines. Each cell unit consists of a plurality of memory cells which are connected in series, each having its source coupled to the drain of the immediately adjacent memory cell. In most NAND-type EEPROMs, each memory cell is of FETMOS structure. To write/read data into/from any memory cell, a voltage higher than the supply voltage is applied to the memory cell. Data is stored into the memory cell by applying a tunnel current or the like is applied to the cell, thereby controlling the electric charge in the charge-accumulating layer of the cell.
Data is written into, and erased from, the NAND-type EEPROM, in the following way. Data is sequentially written into the memory cells of each unit, first into the cell remotest from the bit line (i.e., the cell nearest the source line). A high voltage Vpp (=about 20 V) is applied to the control gate of a selected memory cell. At the same time, an intermediate voltage VppM (=about 10 V) is applied to the control gate and selection gate of the adjacent memory cell located closer to the bit line than the selected memory cell. Simultaneously, 0 V or the intermediate voltage VppM is applied to the bit line, depending on the value of the data to be written into the memory cell.
When 0 V is applied to the bit line, the potential of the bit line is applied to the drain of the memory cell. Electrons are injected from the drain into the floating gate of the memory cell, thereby the threshold voltage of the memory cell shifts to the positive direction. As a result, a "1" bit is written into the memory cell. When the intermediate voltage is applied to the bit line, the potential of the bit line is not applied to the drain of the memory cell. In this case, no electrons are injected from the drain into the floating gate of the memory cell, the threshold voltage of the memory cell does not change, and the memory cell keeps a "0" bit.
Data erase operation is performed, simultaneously from all memory cells. More precisely, all control gates and all selection gates are set at 0 V, and all bit lines and all source lines are set into floating state. Then, the high voltage of 20 V is applied to the p-type well and the n-type substrate. Electrons are thereby injected into the p-type well from the floating gate of every memory cell. The threshold voltage of every memory cell shifts to the negative direction, whereby data is erased.
As can be understood from the above, with an EEPROM driven by a single source supply it is necessary to generate a voltage higher than the supply voltage. To generate this high voltage, a charge pump circuit is incorporated in the EEPROM. To drive the charge pump circuit, a ring oscillator is incorporated in the EEPROM. Generally, the current-drivability of the charge pump circuit decreases as the supply voltage falls. The oscillating frequency of the ring oscillator decreases as the as the supply voltage falls. If designed to operate with a minimal supply voltage, the charge pump circuit will have an excessive current-drivability when applied with a maximal supply voltage. The charge pump circuit would therefore waste power in the NAND-type EEPROM.
In order to solve the above-mentioned problems, the inventors hereof have invented a novel EEPROM. The EEPROM comprises an oscillation circuit and a charge pump circuit. The oscillation circuit has an oscillating frequency which increases as the supply voltage falls. The charge pump circuit has current-applying ability which depends on the oscillating frequency and can increase the supply voltage to generate a voltage high enough to write data into and erase data from the memory cells. The voltage of the charge pump circuit does not influenced by the fluctuation of the supply voltage, and power is not wasted as the supply voltage varies when data is written into/erased from the memory cells.
The transistors used in the oscillation circuit have each a conductance and a threshold voltage which differ from the design values due to the level of the existing manufacturing technology. Inevitably, the oscillating frequency of the oscillation circuit is likely to fluctuate. Furthermore, the oscillating frequency changes with the temperature since the conductance and threshold voltage of each transistor depend upon temperature. The fluctuation of the oscillating frequency results in wasting of power also in the EEPROM invented by the inventors.